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Till now we have dealt with transistor level issues involved in designing a gate and studied the effects on the waveforms on changing various parameters of transistor(length and width) .The graphs we have seen till now will gives the corresponding analog output voltages. In the earlier experiments, when a transistor was placed and connections were made a spice code was written in the back end. We learned spice in the previous experiment . Now we proceed towards digital level designing of circuits for example lets take an or gate in the second experiment was we arranged pmos and nmos in a particular fashion and simulated to obtain a graph , changing the parameters we analyzed how the rise time ,fall time ,delay etc. changes. If you observe the graph you will find that the input changes from low value near 0 V to high value near 5V ,the rise is not steep one but gradual . In digital designing we will bother only about two levels 0 and 1(a threshold is determined i.e. voltages below threshold will be 0 and those above will be 1 )As we move towards digital designing we shift our concerns from how does the analog voltage changes to how to generate a desired output from a given sequence of inputs. For instance now we will visualize gate as an entity which will gives the desired truth table.


Primarily digital designing problem will be of this sort that we expect a certain kind of inputs to yield some output, our aim will be to design a system that will behave accordingly. VHDL is a language to describe such a system.




VHDL stands for VHSIC hardware description language.VHSIC means very-high-speed integrated circuit.As the name suggests it is a hardware description language used to model a digital system.VHDL is commonly used to write text models that describe a logic circuit. VHDL is a Dataflow language, (i.e. models a program as a directed graph of the data flowing between operations). unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time.VHDL is a language that can be understood by hardware


A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).


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